sli4_skh_iscsi.h

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/*
 * Copyright (c) 2011-2015, Emulex
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 *
 * 3. Neither the name of the copyright holder nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 */

/**
 * @file
 * Define iSCSI SLI-4 structures and function prototypes; Skyhawk ASIC
 */

#ifndef _SLI4_SKH_ISCSI_H
#define _SLI4_SKH_ISCSI_H

/**
 * @brief COMMON_GET_SLI4_PARAMETERS
 *
 */
typedef struct sli4_skh_req_common_get_sli4_parameters_s {
    sli4_req_hdr_t  hdr;
} sli4_skh_req_common_get_sli4_parameters_t;


typedef struct sli4_skh_res_common_get_sli4_parameters_s {
    sli4_res_hdr_t  hdr;
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t    protocol_type:8,    /* offset 0x00 */
            :24;
    uint32_t    ft:1,               /* offset 0x04 */
            :3,
            sli_revision:4,
            sli_family:4,
            if_type:4,
            sli_hint_1:8,
            sli_hint_2:5,
            :3;
    uint32_t    eq_page_cnt:4,      /* offset 0x08 */
            :4,
            eqe_sizes:4,
            :4,
            eq_page_sizes:8,
            eqe_count_method:4,
            :4;
    uint32_t    eqe_count_mask:16,  /* offset 0x0C */
            :16;
    uint32_t    cq_page_cnt:4,      /* offset 0x10 */
            :4,
            cqe_sizes:4,
            :2,
            cqv:2,
            cq_page_sizes:8,
            cqe_count_method:4,
            :4;
    uint32_t    cqe_count_mask:16,  /* offset 0x14 */
            :16;
    uint32_t    mq_page_cnt:4,      /* offset 0x18 */
            :10,
            mqv:2,
            mq_page_sizes:8,
            mqe_count_method:4,
            :4;
    uint32_t    mqe_count_mask:16,  /* offset 0x1C */
            :16;
    uint32_t    wq_page_cnt:4,      /* offset 0x20 */
            :4,
            wqe_sizes:4,
            :2,
            wqv:2,
            wq_page_sizes:8,
            wqe_count_method:4,
            :4;
    uint32_t    wqe_count_mask:16,  /* offset 0x24 */
            :16;
    uint32_t    rq_page_cnt:4,      /* offset 0x28 */
            :4,
            rqe_sizes:4,
            :2,
            rqv:2,
            rq_page_sizes:8,
            rqe_count_method:4,
            :4;
    uint32_t    rqe_count_mask:16,       /* offset 0x2C */
            :12,
            rq_db_window:4;
    uint32_t    sglc:1,                  /* offset 0x30 */
            ppdu:1,
            t10pi:1,
            sglr:1,
            :18,
            timm:1,
            tsmm:1,
            :4,
            loopback_scope:4;
    uint32_t    sge_supported_length; /* offset 0x34 */
    uint32_t    sgl_page_cnt:4,       /* offset 0x38 */
            :4,
            sgl_page_sizes:8,
            sgl_pp_align:8,
            :8;
    uint32_t    min_rq_buffer_size:16, /* offset 0x3C */
            :16;
    uint32_t    max_rq_buffer_size;    /* offset 0x40 */
    uint32_t    max_phy_icd:16,        /* offset 0x44 */
            max_phy_conn:16;
    uint32_t    frg_num_field_offset:16, /* offset 0x48 */
            frg_num_field_size:16;
    uint32_t    sgl_idx_field_offset:16, /* offset 0x4C */
            sgl_idx_field_size:16;
    uint32_t    chain_sge_init_1;             /* offset 0x50 */
    uint32_t    chain_sge_init_0;             /* offset 0x54 */
#else
#error big endian version not defined
#endif
} sli4_skh_res_common_get_sli4_parameters_t;

/**
 * @brief WQE used to for INITIATOR_WRITE_COMMAND WQE (data from ini->Tgt)
 */
typedef struct sli4_skh_wqe_ini_write_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t  exp_xfer_len:25,
          :2,
          type:5;
    uint32_t  next_wqe:8,
          wrb_index:8,
          lun:16;
    uint32_t  icd_index:16,
          :16;
    uint32_t  rsvd1;
    uint32_t  bhs_addr_high;
    uint32_t  bhs_addr_low;
    uint32_t  rsvd2;
    uint32_t  cmdsn;
    uint32_t  sge0_addr_high;
    uint32_t  sge0_addr_low;
    uint32_t  sge0_offset:24,
          :7,
          s0l:1;
    uint32_t  sge0_length:17,
          :7,
          dif_enable:1,
          :2,
          inv:1,
          dsp:1,
          :3;
    uint32_t  sge1_addr_high;
    uint32_t  sge1_addr_low;
    uint32_t  sge1_offset:24,
          :7,
          s1l:1;
    uint32_t  sge1_length:17,
          :15;
#else
#error big endian version not defined
#endif
} sli4_skh_wqe_ini_write_t;


/**
 * @brief WQE used to for INITIATOR_TMF WQE
 */
typedef struct sli4_skh_wqe_ini_tmf_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t  :27,
          type:5;
    uint32_t  next_wqe:8,
          wrb_index:8,
          lun:16;
    uint32_t  icd_index:16,
          ref_icd_index:16;
    uint32_t  rsvd1;
    uint32_t  bhs_addr_high;
    uint32_t  bhs_addr_low;
    uint32_t  rsvd2;
    uint32_t  cmdsn;
    uint32_t  rsvd3[3];
    uint32_t  :27,
          inv:1,
          :4;
    uint32_t  rsvd4[4];
#else
#error big endian version not defined
#endif
} sli4_skh_wqe_ini_tmf_t;


/**
 * @brief WQE used to for INITIATOR_NOP_OUT WQE (data from ini->Tgt)
 */
typedef struct sli4_skh_wqe_ini_nop_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t  exp_xfer_len:25,
          :2,
          type:5;
    uint32_t  next_wqe:8,
          wrb_index:8,
          :16;
    uint32_t  icd_index:16,
          :16;
    uint32_t  rsvd1;
    uint32_t  bhs_addr_high;
    uint32_t  bhs_addr_low;
    uint32_t  rsvd2;
    uint32_t  cmdsn;
    uint32_t  sge0_addr_high;
    uint32_t  sge0_addr_low;
    uint32_t  sge0_offset:24,
          :7,
          s0l:1;
    uint32_t  sge0_length:17,
          :10,
          inv:1,
          dsp:1,
          dm:1,
          :2;
    uint32_t  sge1_addr_high;
    uint32_t  sge1_addr_low;
    uint32_t  sge1_offset:24,
          :7,
          s1l:1;
    uint32_t  sge1_length:17,
          :15;
#else
#error big endian version not defined
#endif
} sli4_skh_wqe_ini_nop_t;


/**
 * @brief WQE used to for INITIATOR_READ WQE (data from ini->Tgt)
 */
typedef struct sli4_skh_wqe_ini_read_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t  exp_xfer_len:25,
          :2,
          type:5;
    uint32_t  next_wqe:8,
          wrb_index:8,
          lun:16;
    uint32_t  icd_index:16,
          :16;
    uint32_t  rsvd1;
    uint32_t  bhs_addr_high;
    uint32_t  bhs_addr_low;

    /* Avoid CQ per Connection in Initiator
     */
    uint32_t  rsvd2;
    uint32_t  cmdsn;
    uint32_t  sge0_addr_high;
    uint32_t  sge0_addr_low;
    uint32_t  sge0_offset:24,
          :7,
          s0l:1;
    uint32_t  sge0_length:17,
          :10,
          inv:1,
          :4;
    uint32_t  sge1_addr_high;
    uint32_t  sge1_addr_low;
    uint32_t  sge1_offset:24,
          :7,
          s1l:1;
    uint32_t  sge1_length:17,
          :15;
#else
#error big endian version not defined
#endif
} sli4_skh_wqe_ini_read_t;


/**
 * @@@ TODO: Skyhawk structure definition not yet ready.
 * @brief WQE used to Update a connection context
 */
typedef struct sli4_skh_wqe_context_update_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t max_burst:24,
         :3,
         type:5;

    uint32_t next_wqe:8,
         wrb_index:8,
         :16;

    uint32_t max_send_dsl:24,
         :8;

    uint32_t first_burst:24,
        :8;

    uint32_t max_r2t:16,
         :1,
         header_digest_enable:1,
         data_digest_enable:1,
         error_recovery_level:2,
         :6,
         immediate_data:1,
         initial_r2t:1,
         :3;

    uint32_t statsn;

    uint32_t rsvd1[2];

    uint32_t max_recv_dsl:24,
         :8;

    uint32_t rsvd2[2];

    uint32_t max_cxns:16,
         :11,
         invl:1,
         :1,
         dm:1,
        data_seq_inorder:1,
        data_pdu_inorder:1;

    uint32_t rsvd3[4];
#else
#error big endian version not defined
#endif
} sli4_skh_wqe_context_update_t;

/**
 * @brief WQE used to for TGT_STS WQE (data from ini->Tgt)
 */
typedef struct sli4_skh_wqe_tgt_sts_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t  exp_xfer_len:25,
          :2,
          type:5;

    uint32_t  next_wqe:8,
          wrb_index:8,
          lun:16;

    uint32_t  icd_index:16,
          ref_icd_index:16;

    uint32_t  exp_data_sn;
    uint32_t  bhs_addr_high;
    uint32_t  bhs_addr_low;

    // Use cq per connection.
    uint32_t  :16,
          cq_id:16;

    uint32_t  itt;
    uint32_t  rsvd1[2];

    uint32_t  r2t_offset:24,
          :8;

    uint32_t  :24,
          dif_enable:1,
          :2,
          inv:1,
          :4;

    uint32_t  rsvd2[3];

    uint32_t  rsvd4;

#else
#error big endian version not defined
#endif
} sli4_skh_wqe_tgt_sts_t;


/**
 * @brief WQE used to for TGT_DATAIN WQE (data from Tgt->Ini)
 */
typedef struct sli4_skh_wqe_tgt_datain_s {
#if BYTE_ORDER == LITTLE_ENDIAN

    uint32_t  exp_xfer_len:25,
          :2,
          type:5;
    uint32_t  next_wqe:8,
          wrb_index:8,
          lun:16;
    uint32_t  icd_index:16,
          ref_icd_index:16;
    uint32_t  data_sn;
    uint32_t  bhs_addr_high;
    uint32_t  bhs_addr_low;

    // Use cq per connection.
    uint32_t  :16,
          cq_id:16;
    uint32_t  cmdsn;
    uint32_t  sge0_addr_high;
    uint32_t  sge0_addr_low;
    uint32_t  sge0_offset:24,
          :7,
          s0l:1;
    uint32_t  sge0_length:17,
          :8,
          underrun:1,
          overrun:1,
          inv:1,
          dsp:1,
          dm:1,
          piggy_back_status:1,
          :1;
    uint32_t  sge1_addr_high;
    uint32_t  sge1_addr_low;
    uint32_t  sge1_offset:24,
          :7,
          s1l:1;
    uint32_t  sge1_length:17,
          :15;

#else
#error big endian version not defined
#endif
} sli4_skh_wqe_tgt_datain_t;

/**
 * @brief WQE used to for DIF WQE
 */
typedef struct sli4_skh_wqe_dif_s {
#if BYTE_ORDER == LITTLE_ENDIAN

    uint32_t  exp_xfer_len:25,
          :2,
          type:5;

    uint32_t  next_wqe:8,
          wrb_index:8,
          lun:16;

    uint32_t  icd_index:16,
          ref_icd_index:16;

    uint32_t  data_sn;
    uint32_t  bhs_addr_high;
    uint32_t  bhs_addr_low;
    uint32_t  exp_ref_tag;
    uint32_t  cmdsn;
    uint32_t  sge0_addr_high;
    uint32_t  sge0_addr_low;

    uint32_t  sge0_offset:24,
          :4,
          t10_crc_seed:1,
          t10_atrt:1,
          t10_at:1,
          s0l:1;

    uint32_t  sge0_length:17,
          :6,
          sdm:1,
          dif_enable:1,
          underrun:1,
          overrun:1,
          inv:1,
          dsp:1,
          dm:1,
          piggy_back_status:1,
          :1;

    uint32_t  mkaddr_addr_high;
    uint32_t  mkaddr_addr_low;
    uint32_t  rep_ref_tag;

    uint32_t  meta_tag:16,
          dif_blk_size:3,
          dif_auto_inc:1,
          check_meta_tag:1,
          check_ref_tag:1,
          check_crc:1,
          replace_ref_tag:1,
          rx_dif_mode:4,  //Use reserved for data-ins
          tx_dif_mode:4;
#else
#error big endian version not defined
#endif
} sli4_skh_wqe_dif_t;



/**
 * @brief WQE used to for TGT_SOS WQE (Tgt Response)
 */
typedef struct sli4_skh_wqe_tgt_sos_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t  exp_xfer_len:25,
          :2,
          type:5;
    uint32_t  next_wqe:8,
          wrb_index:8,
          lun:16;
    uint32_t  icd_index:16,
          :16;
    uint32_t  rsvd;
    uint32_t  bhs_addr_high;
    uint32_t  bhs_addr_low;

    // Use cq per connection.
    uint32_t  :16,
          cq_id:16;
    uint32_t  cmdsn;
    uint32_t  sge0_addr_high;
    uint32_t  sge0_addr_low;
    uint32_t  sge0_offset:24,
          :7,
          s0l:1;
    uint32_t  sge0_length:17,
          :10,
          inv:1,
          dsp:1,
          dm:1,
          piggy_back_status:1,
          :1;
    uint32_t  sge1_addr_high;
    uint32_t  sge1_addr_low;
    uint32_t  sge1_offset:24,
          :7,
          s1l:1;
    uint32_t  sge1_length:17,
          :15;
#else
#error big endian version not define
#endif
} sli4_skh_wqe_tgt_sos_t;


/**
 * @brief WQE used to transmit a PDU without any modificiation (TGT_DM_CMD)
 */
typedef struct sli4_skh_wqe_unassisted_s {
#if BYTE_ORDER == LITTLE_ENDIAN

    uint32_t  exp_xfer_len:25,
          :2,
          type:5;
    uint32_t  next_wqe:8,
          wrb_index:8,
          :16;
    uint32_t  icd_index:16,
          :16;
    uint32_t  rsvd;
    uint32_t  bhs_addr_high;
    uint32_t  bhs_addr_low;

    // Use cq per connection.
    uint32_t  :16,
          cq_id:16;
    uint32_t  login_pdu;
    uint32_t  sge0_addr_high;
    uint32_t  sge0_addr_low;
    uint32_t  sge0_offset:24,
          :7,
          s0l:1;
    uint32_t  sge0_length:17,
          :10,
          inv:1,
          dsp:1,
          dm:1,
          piggy_back_status:1,
          :1;
    uint32_t  sge1_addr_high;
    uint32_t  sge1_addr_low;
    uint32_t  sge1_offset:24,
          :7,
          s1l:1;
    uint32_t  sge1_length:17,
          :15;

#else
#error big endian version not defined
#endif
} sli4_skh_wqe_unassisted_t;


/**
 * @brief Used to decode DMSG CQEs.
 */
typedef struct sli4_skh_iscsi_i_t_dmsg_cqe_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t  ack_num;
    uint32_t  pdu_bytes_rcvd;
    uint32_t  code:6,
          :10,
          wqe_index:16;
    uint32_t  rsvd:16,
          cid:13,
          rsvd1:2,
          valid:1;
#else
#error big endian version not defined
#endif
} sli4_skh_iscsi_i_t_dmsg_cqe_t;

/**
 * @brief Used to decode DPDU CQEs.
 */
typedef struct sli4_skh_iscsi_i_t_dpdu_cqe_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t  def_buf_addr_high;
    uint32_t  def_buf_addr_low;
    uint32_t  code:6,
          num_consumed:9,
          data_length:17;
    uint32_t  rq_index:16,
          cid:13,
          rsvd:1,
          fin:1,
          valid:1;
#else
#error big endian version not defined
#endif
} sli4_skh_iscsi_i_t_dpdu_cqe_t;

/**
 * @brief Used to decode I_SOL CQEs.
 */
typedef struct sli4_skh_iscsi_i_sol_cqe_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t hw_sts:8,
         status_or_response:8,
         wqe_index:16;
    uint32_t expcmdsn;
    uint32_t code:6,
         is_sts_or_rsp:1,
         rsvd:1,
         cmd_window:8,
         cid:13,
         underrun:1,
         overrun:1,
         sts:1;
    uint32_t residual:31,
         valid:1;
#else
#error big endian version not defined
#endif
} sli4_skh_iscsi_i_sol_cqe_t;

/**
 * @brief Used to decode T_SOL CQEs.
 */
typedef struct sli4_skh_iscsi_t_sol_cqe_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t  hw_sts:8,
          :24;
    uint32_t  pdu_bytes_rcvd;
    uint32_t  code:6,
          :26;
    uint32_t  wqe_index:16,
          cid:13,
          :2,
          valid:1;
#else
#error big endian version not defined
#endif
} sli4_skh_iscsi_t_sol_cqe_t;

/**
 * @brief Used to decode T_SOL_DATA_DIGEST CQEs.
 */
typedef struct sli4_skh_iscsi_t_sol_data_digest_cqe_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t  datasn:12,
          :4,
          sgl_icd_index:16;
    uint32_t  exp_statsn;
    uint32_t  code:6,
          buffer_offset:24,
          fin:1,
          :1;
    uint32_t  data_seg_len:17,
          cid:13,
          :1,
          valid:1;
#else
#error big endian version not defined
#endif
} sli4_skh_iscsi_t_sol_data_digest_cqe_t;

/**
 * @brief Used to decode CNXINV CQEs.
 */
typedef struct sli4_skh_iscsi_t_cnxinv_cqe_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t  def_buf_addr_high;
    uint32_t  def_buf_addr_low;
    uint32_t  code:6,
          :10,
          rq_index:16;
    uint32_t  partial_dsl:17,
          cid:13,
          :1,
          valid:1;
#else
#error big endian version not defined
#endif
} sli4_skh_iscsi_t_cnxinv_cqe_t;

/**
 * @brief Used to decode CMNDINV CQEs.
 */
typedef struct sli4_skh_iscsi_t_cmndinv_cqe_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t  rsvd0;
    uint32_t  rsvd1;
    uint32_t  code:6,
          :26;
    uint32_t  sgl_icd_index:16,
          cid:13,
          :2,
          valid:1;
#else
#error big endian version not defined
#endif
} sli4_skh_iscsi_t_cmndinv_cqe_t;

/**
 * @brief Used to decode T_SOL_DATA_DIGEST CQEs.
 */
typedef struct sli4_skh_iscsi_tx_dif_error_cqe_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t  dif_error:8,
          :24;
    uint32_t  resv;
    uint32_t  code:6,
          :26;
    uint32_t  icd_index:16,
          cid:13,
          :2,
          valid:1;
#else
#error big endian version not defined
#endif
} sli4_skh_iscsi_tx_dif_error_cqe_t;

extern cqe_handler_t *ini_skh_cqe_handlers[ISCSI_CQE_CODE_MAX+1];
extern cqe_handler_t *tgt_skh_cqe_handlers[ISCSI_CQE_CODE_MAX+1];
extern sli_wqe_handlers_t sli_skh_iscsi_wqe_handlers;
extern int32_t sli_skh_get_sli4_parameters(sli4_t *sli4);

#endif /* !_SLI4_SKH_ISCSI_H */

/* vim: set noexpandtab textwidth=120: */