sli4_be3_iscsi.h

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/*
 * Copyright (c) 2011-2015, Emulex
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 *
 * 3. Neither the name of the copyright holder nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 */

/**
 * @file
 * Define iSCSI SLI-4 structures and function prototypes (BE3: Blade Engine 3)
 */

#ifndef _SLI4_BE3_ISCSI_H
#define _SLI4_BE3_ISCSI_H

/**
 * @brief WQE used to for INITIATOR_WRITE_COMMAND WQE (data from ini->Tgt)
 */
typedef struct sli4_be3_wqe_ini_write_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t lun:14,
         :1,
         inv:1,
         wrb_index:8,
         dsp:1,
         :3,
         type:4;

    uint32_t next_wqe:8,
         exp_xfer_len:24;

    uint32_t icd_index:16,
         :16;

    uint32_t rsvd1;
    uint32_t bhs_addr_high;
    uint32_t bhs_addr_low;
    uint32_t cmdsn;
    uint32_t dif_ref_tag;
    uint32_t sge0_addr_high;
    uint32_t sge0_addr_low;

    uint32_t sge0_offset:22,
         :1,
         dif_mode:2,
         dif_blk_size:3,
         :3,
         s0l:1;

    uint32_t sge0_length:17,
         :15;

    uint32_t sge1_addr_high;
    uint32_t sge1_addr_low;

    uint32_t sge1_offset:22,
         :9,
         s1l:1;

    uint32_t sge1_length:17,
         :15;
#else
#error big endian version not defined
#endif
} sli4_be3_wqe_ini_write_t;


/**
 * @brief WQE used to for INITIATOR_TMF WQE
 */
typedef struct sli4_be3_wqe_ini_tmf_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t lun:14,
         :1,
         inv:1,
         wrb_index:8,
         :4,
         type:4;

    uint32_t next_wqe:8,
         :24;

    uint32_t icd_index:16,
         :16;

    uint32_t rsvd1;
    uint32_t bhs_addr_high;
    uint32_t bhs_addr_low;
    uint32_t cmdsn;
    uint32_t rsvd2[9];
#else
#error big endian version not defined
#endif
} sli4_be3_wqe_ini_tmf_t;


/**
 * @brief WQE used to for INITIATOR_NOP_OUT WQE (data from ini->Tgt)
 */
typedef struct sli4_be3_wqe_ini_nop_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t rsvd1:15,
         inv:1,
         wrb_index:8,
         dsp:1,
         dm:1,
         :2,
         type:4;
    uint32_t next_wqe:8,
         exp_xfer_len:24;
    uint32_t icd_index:16,
         :16;
    uint32_t rsvd2;
    uint32_t bhs_addr_high;
    uint32_t bhs_addr_low;
    uint32_t cmdsn;
    uint32_t rsvd3;
    uint32_t sge0_addr_high;
    uint32_t sge0_addr_low;
    uint32_t sge0_offset:22,
         :9,
         s0l:1;
    uint32_t sge0_length:17,
         :15;
    uint32_t sge1_addr_high;
    uint32_t sge1_addr_low;
    uint32_t sge1_offset:22,
         :9,
         s1l:1;
    uint32_t sge1_length:17,
         :15;
#else
#error big endian version not defined
#endif
} sli4_be3_wqe_ini_nop_t;


/**
 * @brief WQE used to for INITIATOR_READ WQE (data from ini->Tgt)
 */
typedef struct sli4_be3_wqe_ini_read_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t lun:14,
         :1,
         inv:1,
         wrb_index:8,
         :4,
         type:4;

    uint32_t next_wqe:8,
         exp_xfer_len:24;

    uint32_t icd_index:16,
         :16;

    uint32_t rsvd1;
    uint32_t bhs_addr_high;
    uint32_t bhs_addr_low;
    uint32_t cmdsn;
    uint32_t dif_ref_tag;
    uint32_t sge0_addr_high;
    uint32_t sge0_addr_low;

    uint32_t sge0_offset:22,
         :1,
         dif_mode:2,
         dif_blk_size:3,
         :3,
         s0l:1;

    uint32_t sge0_length:17,
         :15;

    uint32_t sge1_addr_high;
    uint32_t sge1_addr_low;

    uint32_t sge1_offset:22,
         :9,
         s1l:1;

    uint32_t sge1_length:17,
         :15;
#else
#error big endian version not defined
#endif
} sli4_be3_wqe_ini_read_t;


/**
 * @brief WQE used to Update a connection context
 */
typedef struct sli4_be3_wqe_context_update_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t rsvd0:16,
         wrb_index:8,
         :1,
         dm:1,
         :2,
         type:4;

    uint32_t next_wqe:8,
         max_burst:19,
         :5;

    uint32_t rsvd1:15,
         max_recv_dsl:17;

    uint32_t first_burst:14,
         :18;

    uint32_t rsvd2:17,
         header_digest_enable:1,
         data_digest_enable:1,
         error_recovery_level:2,
         :6,
         immediate_data:1,
         initial_r2t:1,
         :3;

    uint32_t statsn;
    uint32_t rsvd3[10];
#else
#error big endian version not defined
#endif
} sli4_be3_wqe_context_update_t;

/**
 * @brief WQE used to for TGT_STS WQE (data from ini->Tgt)
 */
typedef struct sli4_be3_wqe_tgt_sts_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t lun:14,
         :1,
         inv:1,
         wrb_index:8,
         :4,
         type:4;

    uint32_t next_wqe:8,
         exp_xfer_len:24;

    uint32_t icd_index:16,
         :16;

    uint32_t exp_data_sn;
    uint32_t bhs_addr_high;
    uint32_t bhs_addr_low;
    uint32_t itt;
    uint32_t dif_ref_tag;
    uint32_t rsvd2[2];

    uint32_t rsvd3:23,
         dif_mode:2,
         dif_blk_size:3,
         :4;

    uint32_t rsvd4[3];

    uint32_t r2t_offset:22,
         :10;

    uint32_t rsvd5:17,
         ref_icd_index:12,
         :3;
#else
#error big endian version not defined
#endif
} sli4_be3_wqe_tgt_sts_t;

/**
 * @brief WQE used to for TGT_STS WQE (data from Tgt->Ini)
 */
typedef struct sli4_be3_wqe_tgt_datain_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t lun:14,
         :1,
         inv:1,
         wrb_index:8,
         dsp:1,
         dm:1,
         underrun:1,
         overrun:1,
         type:4;

    uint32_t next_wqe:8,
         exp_xfer_len:24;

    uint32_t icd_index:16,
         :16;

    uint32_t data_sn;
    uint32_t bhs_addr_high;
    uint32_t bhs_addr_low;
    uint32_t rsvd1;
    uint32_t dif_ref_tag;
    uint32_t sge0_addr_high;
    uint32_t sge0_addr_low;

    uint32_t sge0_offset:22,
         piggy_back_status:1,
         dif_mode:2,
         dif_blk_size:3,
         :3,
         s0l:1;

    uint32_t sge0_length:17,
         :15;

    uint32_t sge1_addr_high;
    uint32_t sge1_addr_low;

    uint32_t sge1_offset:22,
         :9,
         s1l:1;

    uint32_t sge1_length:17,
         ref_icd_index:12,
         :3;
#else
#error big endian version not defined
#endif
} sli4_be3_wqe_tgt_datain_t;

/**
 * @brief WQE used to for TGT_SOS WQE (Tgt Response)
 */
typedef struct sli4_be3_wqe_tgt_sos_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t    lun:14,
        :1,
        inv:1,
        wrb_index:8,
        dsp:1,
        dm:1,
        :2,
        type:4;
    uint32_t    next_wqe:8,
        exp_xfer_len:24;
    uint32_t    icd_index:16,
        :16;
    uint32_t    rsvd0;
    uint32_t    bhs_addr_high;
    uint32_t    bhs_addr_low;
    uint32_t    rsvd1[2];
    uint32_t    sge0_addr_high;
    uint32_t    sge0_addr_low;
    uint32_t    sge0_offset:22,
        piggy_back_status:1, /* Used to incr statSN */
        :8,
        s0l:1;
    uint32_t    sge0_length:17,
        :15;
    uint32_t    sge1_addr_high;
    uint32_t    sge1_addr_low;
    uint32_t    sge1_offset:22,
        :9,
        s1l:1;
    uint32_t    sge1_length:17,
        :15;
#else
#error big endian version not defined
#endif
} sli4_be3_wqe_tgt_sos_t;


/**
 * @brief WQE used to transmit a PDU without any modificiation
 */
typedef struct sli4_be3_wqe_unassisted_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t rsvd0:15,
         inv:1,
         wrb_index:8,
         dsp:1,
         dm:1,
         :2,
         type:4;

    uint32_t next_wqe:8,
         exp_xfer_len:24;

    uint32_t icd_index:16,
         :16;

    uint32_t rsvd1;
    uint32_t bhs_addr_high;
    uint32_t bhs_addr_low;
    uint32_t login_pdu;
    uint32_t rsvd2;
    uint32_t sge0_addr_high;
    uint32_t sge0_addr_low;

    uint32_t sge0_offset:22,
         piggy_back_status:1, /* Used to incr statSN */
         :8,
         s0l:1;

    uint32_t sge0_length:17,
         :15;

    uint32_t sge1_addr_high;
    uint32_t sge1_addr_low;

    uint32_t sge1_offset:22,
         :9,
         s1l:1;

    uint32_t sge1_length:17,
         :15;
#else
#error big endian version not defined
#endif
} sli4_be3_wqe_unassisted_t;

/**
 * @brief Used to decode DMSG CQEs.
 */
typedef struct sli4_be3_iscsi_i_t_dmsg_cqe_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t ack_num;
    uint32_t pdu_bytes_rcvd;

    uint32_t code:6,
         cid:10,
         wqe_index:8,
         :8;

    uint32_t rsvd:31,
         valid:1;
#else
#error big endian version not defined
#endif
} sli4_be3_iscsi_i_t_dmsg_cqe_t;

/**
 * @brief Used to decode DPDU CQEs.
 */
typedef struct sli4_be3_iscsi_i_t_dpdu_cqe_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t def_buf_addr_high;
    uint32_t def_buf_addr_low;

    uint32_t code:6,
         cid:10,
         data_length:16;

    uint32_t rq_index:16,
         num_consumed:10,
         :4,
         fin:1,
         valid:1;
#else
#error big endian version not defined
#endif
} sli4_be3_iscsi_i_t_dpdu_cqe_t;

/**
 * @brief Used to decode I_SOL CQEs.
 */
typedef struct sli4_be3_iscsi_i_sol_cqe_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t hw_sts:2,
         :4,
         cid_high:2,
         status:8,
         response:8,
         flags:7,
         sts:1;

    uint32_t expcmdsn;

    uint32_t code:6,
         cid:10,
         wqe_index:8,
         cmd_window:8;

    uint32_t residual:31,
         valid:1;
#else
#error big endian version not defined
#endif
} sli4_be3_iscsi_i_sol_cqe_t;

/**
 * @brief Used to decode T_SOL CQEs.
 */
typedef struct sli4_be3_iscsi_t_sol_cqe_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t hw_sts:2,
         :4,
         cid_high:2,
         :24;

    uint32_t rsvd;

    uint32_t code:6,
         cid:10,
         :16;

    uint32_t wqe_index:8,
         :23,
         valid:1;
#else
#error big endian version not defined
#endif
} sli4_be3_iscsi_t_sol_cqe_t;

/**
 * @brief Used to decode T_SOL_DATA_DIGEST CQEs.
 */
typedef struct sli4_be3_iscsi_t_sol_data_digest_cqe_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t buffer_offset;
    uint32_t exp_statsn;

    uint32_t code:6,
         cid:10,
         datasn:12,
         cid_high:2,
         fin:1,
         :1;

    uint32_t data_seg_len:17,
         :2,
         sgl_icd_index:12,
         valid:1;
#else
#error big endian version not defined
#endif
} sli4_be3_iscsi_t_sol_data_digest_cqe_t;

/**
 * @brief Used to decode CNXINV CQEs.
 */
typedef struct sli4_be3_iscsi_t_cnxinv_cqe_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t def_buf_addr_high;
    uint32_t def_buf_addr_low;

    uint32_t code:6,
         cid:10,
         rq_index:16;

    uint32_t partial_dsl:17,
         :14,
         valid:1;
#else
#error big endian version not defined
#endif
} sli4_be3_iscsi_t_cnxinv_cqe_t;

/**
 * @brief Used to decode CMNDINV CQEs.
 */
typedef struct sli4_be3_iscsi_t_cmndinv_cqe_s {
#if BYTE_ORDER == LITTLE_ENDIAN
    uint32_t rsvd0;
    uint32_t rsvd1;

    uint32_t code:6,
         cid:10,
         :16;

    uint32_t sgl_icd_index:12,
         :19,
         valid:1;
#else
#error big endian version not defined
#endif
} sli4_be3_iscsi_t_cmndinv_cqe_t;

extern cqe_handler_t *ini_be3_cqe_handlers[ISCSI_CQE_CODE_MAX+1];
extern cqe_handler_t *tgt_be3_cqe_handlers[ISCSI_CQE_CODE_MAX+1];
extern sli_wqe_handlers_t sli_be3_iscsi_wqe_handlers;
extern int32_t sli_be3_get_sli4_parameters(sli4_t *sli4);

#endif /* !_SLI4_BE3_ISCSI_H */

/* vim: set noexpandtab textwidth=120: */